1. Field of the Invention
This invention relates to non-volatile semiconductor memories such as EPROM, EEPROM, and flash memory, and more particularly to memory architectures that provide high data transfer rates.
2. Description of Related Art
Semiconductor non-volatile memories such as EPROM, EEPROM, and flash memories, which permit electrical programming and erasing of memory cells, are well known. Such memories conventionally include arrays of memory cells where each memory cell includes a floating gate transistor. Write and erase circuits coupled to an array change the threshold voltages of floating gate transistors by electrically charging or discharging the floating gates of the transistors. In particular, to write to a memory cell, the write circuit charges the floating gate of the floating gate transistor in the memory cell until the threshold voltage of the transistor is at a level that representing the value being written. The read circuit senses the threshold voltage of a floating gate transistor in a memory cell to determine the value stored in the cell.
In different applications, the threshold voltage of a floating gate transistor can represent a single bit, multiple bits, or an analog value. For conventional binary (i.e., single-bit-per-cell) non-volatile memories, threshold voltages below a break-point level represent one binary value (0 or 1), and threshold voltages above the break-point level represent the other binary value (1 or 0). Accordingly, erase and write circuits in a binary memory set the threshold voltages of every memory cell at either a high level or a low level, and the read circuit can easily distinguish between the levels. Threshold voltages of memory cells in multiple-bits-per-cell memories or analog memories respectively have several (4, 8, 16, or more) distinct threshold voltage bands or a continuous range of levels. Accordingly, multiple-bits-per-cell memories and analog memories need precise control when writing threshold voltages and high accuracy when identifying threshold voltages. The write and read circuits which achieve the precision and accuracy required for multiple-bits-per-cell and analog memories are typically slower than write and read circuits for binary memory. Accordingly, the read and write speeds of read and write circuits in multiple-bit-per-cell memory and analog memory are normally slower than their binary counterparts.
To improve read and write data rates (i.e., the bandwidth) for an analog memory, a memory system using a pair of buffers and multiple write circuits is known. The memory system sequentially collects data in a first buffer while writing in parallel, the data from a second buffer into a memory array. The buffers exchange roles when writing of the data from the second buffer is complete and the first buffer is full of data. Similarly, an analog memory can use a pair of buffers and a set of parallel read circuits to improve read rates. A disadvantage of such memories is increased costs associated with the increases in circuit complexity and integrated circuit area.
U.S. Pat. No. 5,680,341, entitled "Pipelined Record and Playback for Analog Non-Volatile Memory", to Wong. et al., which is hereby incorporated by reference in its entirety, describes memory systems using multiple read or write pipelines. A pipelined write architecture, for example, includes multiple write pipelines with each write pipeline including a sample-and-hold circuit and write circuitry for writing a value from the sample-and-hold circuit into a memory cell. Write pipelines are started sequentially as the sample-and-hold circuits acquire values to be written. By the time the last write pipeline in the sequence starts a write operation, first pipeline in the sequence has completed a previously started write operation and is ready to start another. Accordingly, a pipelined architecture can increase the write bandwidth in proportion to the number of write pipelines employed, without sacrificing accuracy or resolution. A pipeline read architecture can also be used to increase the read bandwidth. An advantage that the pipelined memory architecture has over the parallel read and write architecture is a reduction in required circuitry. In particular, the parallel architecture requires two sample-and-hold circuits (one in each buffer) per read or write circuit. The pipelined architecture requires only a single sample-and-hold circuit per read or write circuit. Thus, the pipelined architecture can reduce circuit cost by decreasing the required integrated circuit area.
Memory architectures which provide a high bandwidth for analog and multiple-bits-per-cell data flow but require even less circuit area are desired.